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8789e?dflash?10/2013 features ? single 1.65v - 3.6v supply ? serial peripheral interface (spi) compatible ? supports spi modes 0 and 3 ? supports rapids ? operation ? continuous read capability through entire array ? up to 85mhz ? low-power read option up to 15mhz ? clock-to-output time (t v ) of 6ns maximum ? user configurable page size ? 256 bytes per page ? 264 bytes per page (default) ? page size can be factory pre-configured for 256 bytes ? one sram data buffer (256/264 bytes) ? flexible programming options ? byte/page program (1 to 256/264 bytes) directly into main memory ? buffer write ? buffer to main memory page program ? flexible erase options ? page erase (256/264 bytes) ? block erase (2kb) ? sector erase (32kb) ? chip erase (2-mbits) ? advanced hardware and software data protection features ? individual sector protection ? individual sector lockdown to make any sector permanently read-only ? 128-byte, one-time programmable (otp) security register ? 64 bytes factory programmed with a unique identifier ? 64 bytes user programmable ? hardware and software controlled reset options ? jedec standard manufacturer and device id read ? low-power dissipation ? 200na ultra-deep power-down current (typical) ? 3 a deep power-down current (typical) ? 25 a standby current (typical at 20mhz) ? 4.5ma active read current (typical) ? endurance: 100,000 program/erase cycles per page minimum ? data retention: 20 years ? complies with full industrial temperature range ? green (pb/halide-free/rohs compliant) packaging options ? 8-lead soic (0.150 ? wide and 0.208" wide) ? 8-pad ultra-thin dfn (5 x 6 x 0.6mm) ? 9-ball ultra-thin ubga (6 x 6 x 0.6mm) at45db021e 2-mbit dataflash (with extra 64-kbits), 1.65v minimum spi serial flash memory
2 at45db021e 8789e?dflash?10/2013 description the adesto ? at45db021e is a 1.65v minimum, serial-interface sequential access flash memory is ideally suited for a wide variety of digital voice, image, program code, and data storage applications. the at45db021e also supports the rapids serial interface for applications requiring very high speed operation. its 2,162,688 bits of memory are organized as 1,024 pages of 256 bytes or 264 bytes each. in addition to the main memory, at45db021e also contains one sram buffer of 256/264 bytes. the buffer can be used as additional system scratch memory, and e 2 prom emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the adesto dataflash ? uses a serial interface to sequentially access its data. the simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. the device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. to allow for simple in-system re-programmability, at45db021e does not require high input voltages for programming. the device operates from a single 1.65v to 3.6v power supply for the erase and program and read operations. the at45db021e is enabled through the chip select pin ( cs) and accessed via a 3-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming and erase cycles are self-timed. 1. pin configurations and pinouts figure 1-1. pinouts note: 1. the metal pad on the bottom of the udfn package is not internally connected to a voltage potential. this pad can be a ?no connect? or connected to gnd. 1 2 3 4 8 7 6 5 si sck reset cs so gnd v cc wp 8-lead soic top view si sck reset cs so gnd v cc wp 8 7 6 5 1 2 3 4 8-pad udfn top view sck gnd v cc wp nc cs so si rst 9-ball ubga top view
3 at45db021e 8789e?dflash?10/2013 table 1-1. pin configurations symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in the standby mode (not deep power-down mode) and the output pin (so) will be in a high-impedance state. when the device is deselected, data will not be accepted on the input pin (si). a high-to-low transition on the cs pin is required to start an operation and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. ? input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. data present on the si pin will be ignored whenever the device is deselected ( cs is deasserted). ? input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. the so pin will be in a high-impedance state whenever the device is deselected ( cs is deasserted). ? output wp write protect: when the wp pin is asserted, all sectors specified for protection by the sector protection register will be protected against program and erase operations regardless of whether the enable sector protection command has been issued or not. the wp pin functions independently of the software controlled protection method. after the wp pin goes low, the contents of the sector protection register cannot be modified. if a program or erase command is issued to the device while the wp pin is asserted, the device will simply ignore the command and perform no operation. the device will return to the idle state once the cs pin has been deasserted. the enable sector protection command and the sector lockdown command will be recognized by the device when the wp pin is asserted. the wp pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input reset reset: a low state on the reset pin ( reset) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature is not utilized, then it is recommended that the reset pin be driven high externally. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? ground
4 at45db021e 8789e?dflash?10/2013 2. block diagram figure 2-1. block diagram flash memory array i/o interface sck cs reset v cc gnd wp so si page (256/264 bytes) buffer 1 (256/264 bytes)
5 at45db021e 8789e?dflash?10/2013 3. memory array to provide optimal flexibility, the at45db021e memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. figure 3-1, memory architecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. program operations to the dataflash can be done at the full page level or at the byte level (a variable number of bytes). the erase operations can be performed at the chip, sector, block, or page level. figure 3-1. memory architecture diagram sector 0a = 8 pages 2,048/2,112 bytes sector 0b = 120 pages 30,720/31,680 bytes block = 2,048/2,112 bytes 8 pages sector 0a sector 0b page = 256/264 bytes page 0 page 1 page 6 page 7 page 8 page 9 page 1,022 page 1,023 block 0 page 14 page 15 page 16 page 17 page 18 block 1 sector architecture block architecture page architecture block 0 block 1 block 14 block 15 block 16 block 17 block 126 block 127 block 30 block 31 block 112 block 113 sector 1 sector 7 sector 7 = 128 pages 32,768/33,792 bytes block 2 sector 1 = 128 pages 32,768/33,792 bytes sector 6 = 128 pages 32,768/33,792 bytes
6 at45db021e 8789e?dflash?10/2013 4. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 15-1 on page 38 through table 15-4 on page 39 . a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. three address bytes are used to address memory locations in either the main memory array or in the buffer. the three address bytes will be comprised of a number of dummy bits and a number of actual device address bits, with the number of dummy bits varying depending on the operation being performed and the selected device page size. buffer addressing for the standard dataflash page size (264 bytes) is referenced in the datasheet using the terminology bfa8 - bfa0 to denote the nine address bits required to designate a byte address within the buffer. the main memory addressing is referenced using the terminology pa9 - pa0 and ba8 - ba0, where pa9 - pa0 denotes the 10 address bits required to designate a page address, and ba8 - ba0 denotes the nine address bits required to designate a byte address within the page. therefore, when using the standard dataflash page size, a total of 22 address bits are used. for the ?power of 2? binary page size (256 bytes), the buffer addressing is referenced in the datasheet using the conventional terminology bfa7 - bfa0 to denote the eight address bits required to designate a byte address within the buffer. main memory addressing is referenced using the terminology a17 - a0, where a17 - a8 denotes the 10 address bits required to designate a page address, and a7 - a0 denotes the eight address bits required to designate a byte address within a page. therefore, when using the binary page size, a total of 21 address bits are used.
7 at45db021e 8789e?dflash?10/2013 5. read commands by specifying the appropriate opcode, data can be read from the main memory or from the data buffer. the dataflash supports rapids protocols for mode 0 and mode 3. please see section 25., "detailed bit-level read waveforms: rapids mode 0/mode 3" on page 55 for diagrams detailing the clock cycle sequences for each mode. 5.1 continuous array read (legacy command: e8h) by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the need for additional address sequences. to perform a continuous array read using the standard dataflash page size (264-bytes), an opcode of e8h must be clocked into the device followed by three address bytes (which comprise the 19-bit page and byte address sequence) and four dummy bytes. the first 10 bits (pa9 - pa0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits (ba8 - ba0) of the 19-bit address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (256 bytes), the opcode e8h must be clocked into the device followed by three address bytes (a17 - a0) and four dummy bytes. the dummy bytes that follow the address bytes are needed to initialize the read operation. following the dummy bytes, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy bytes and the reading of data. when the end of a page in main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses the data buffer and leaves the contents of the buffer unchanged. note: this command is not recommended for new designs. 5.2 continuous array read (high frequency mode: 0bh opcode) this command can be used to read the main memory array sequentially at the highest possible operating clock frequency up to the maximum specified by f car1 . to perform a continuous array read using the standard dataflash page size (264 bytes), the cs pin must first be asserted, and then an opcode of 0bh must be clocked into the device followed by three address bytes and one dummy byte. the first 10 bits (pa9 - pa0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits (ba8 - ba0) of the 19-bit address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (256 bytes), the opcode 0bh must be clocked into the device followed by three address bytes (a17 - a0) and one dummy byte. following the dummy byte, additional clock pulses on the sck pin will result in data being output on the so pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses the data buffer and leaves the contents of the buffer unchanged.
8 at45db021e 8789e?dflash?10/2013 5.3 continuous array read (low frequency mode: 03h opcode) this command can be used to read the main memory array sequentially at lower clock frequencies up to maximum specified by f car2 . unlike the previously described read commands, this continuous array read command for lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. to perform a continuous array read using the standard dataflash page size (264 bytes), the cs pin must first be asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). the first 10 bits (pa9 - pa0) of the 19-bit address sequence specify which page of the main memory array to read, and the last nine bits (ba8 - ba0) of the 19-bit address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (256 bytes), the opcode 03h must be clocked into the device followed by three address bytes (a17 - a0). following the address bytes, additional clock pulses on the sck pin will result in data being output on the so pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car2 specification. the continuous array read bypasses the data buffer and leaves the contents of the buffer unchanged. 5.4 continuous array read (low power mode: 01h opcode) this command is ideal for applications that want to minimize power consumption and do not need to read the memory array at high frequencies. like the 03h opcode, this continuous array read command allows reading the main memory array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. the memory can be read at clock frequencies up to maximum specified by f car3 . to perform a continuous array read using the standard dataflash page size (264 bytes), the cs pin must first be asserted, and then an opcode of 01h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). the first 10 bits (pa9 - pa0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits (ba8 - ba0) of the 19-bit address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (256 bytes), the opcode 01h must be clocked into the device followed by three address bytes (a17 - a0). following the address bytes, additional clock pulses on the sck pin will result in data being output on the so pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the continuous array read is defined by the f car3 specification. the continuous array read bypasses the data buffer and leaves the contents of the buffer unchanged.
9 at45db021e 8789e?dflash?10/2013 5.5 main memory page read a main memory page read allows the user to read data directly from any one of the 1,024 pages in the main memory, bypassing the data buffer and leaving the contents of the buffer unchanged. to start a main memory page read using the standard dataflash page size (264 bytes), the cs pin must first be asserted then an opcode of d2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. the first 10 bits (pa9 - pa0) of the 19-bit address sequence specify which page of the main memory array to read, and the last nine bits (ba8 - ba0) of the 19-bit address sequence specify the starting byte address within the page. to perform a main memory page read with the binary page size (256 bytes), the opcode d2h must be clocked into the device followed by three address bytes (a17 - a0) and four dummy bytes. the first 10 bits (a17 - a8) of the 18-bit address sequence specify which page of the main memory array to read, and the last eight bits (a7 - a0) of the 18-bit address sequence specify the starting byte address within that page. the dummy bytes that follow the address bytes are sent to initialize the read operation. following the dummy bytes, the additional pulses on sck result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. unlike the continuous array read command, when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page rather than the beginning of the next page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses the data buffer and leaves the contents of the buffer unchanged. 5.6 buffer read the data buffer can be accessed independently from the main memory array, and utilizing the buffer read command allows data to be sequentially read directly from the buffer. two opcodes, d4h or d1h, can be used for the buffer read command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the buffer. the d4h opcode can be used at any sck frequency up to the maximum specified by f car while the d1h opcode can be used for lower frequency read operations up to the maximum specified by f car2 . to perform a buffer read using the standard dataflash buffer size (264 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (bfa8 -bfa0). to perform a buffer read using the binary buffer size (256 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 16 dummy bits and eight address bits (a7 - a0). following the address bytes, one dummy byte must be clocked into the device to initialize the read operation if using opcode d4h. the cs must remain low during the loading of the opcode, the address bytes, the dummy byte (for opcode d4h only), and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so).
10 at45db021e 8789e?dflash?10/2013 6. program and erase commands 6.1 buffer write utilizing the buffer write command allows data clocked in from the si pin to be written directly into the data buffer. to load data into the buffer using the standard dataflash buffer size (264 bytes), an opcode of 84h must be clocked into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (bfa8 - bfa0). the nine buffer address bits specify the first byte in the buffer to be written. to load data into the buffer using the binary buffer size (256 bytes), an opcode of 84h must be clocked into the device followed by 16 dummy bits and eight address bits (a7 - a0). the eight address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 6.2 buffer to main memory page program with built-in erase the buffer to main memory page program with built-in erase command allows data that is stored in the buffer to be written into an erased or programmed page in the main memory array. it is not necessary to pre-erase the page in main memory to be written because this command will automatically erase the selected page prior to the program cycle. to perform a buffer to main memory page program with built-in erase using the standard dataflash page size (264 bytes), an opcode of 83h must be clocked into the device followed by three address bytes comprised of five dummy bits,10 page address bits (pa9 - pa0) that specify the page in the main memory to be written, and nine dummy bits. to perform a buffer to main memory page program with built-in erase using the binary page size (256 bytes), an opcode of 83h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) that specify the page in the main memory to be written, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the device will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into that same page in main memory. both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates intelligent erase and program algorithms that can detect when a byte location fails to erase or program properly. if an erase or programming error arises, it will be indicated by the epe bit in the status register. 6.3 buffer to main memory page program without built-in erase the buffer to main memory page program without built-in erase command allows data that is stored in the buffer to be written into a pre-erased page in the main memory array. it is necessary that the page in main memory to be written be previously erased in order to avoid programming errors. to perform a buffer to main memory page program without built-in erase using the standard dataflash page size (264 bytes), an opcode of 88h must be clocked into the device followed by three address bytes comprised of five dummy bits,10 page address bits (pa9 - pa0) that specify the page in the main memory to be written, and nine dummy bits. to perform a buffer to main memory page program using the binary page size (256 bytes), an opcode 88h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) that specify the page in the main memory to be written, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the device will program the data stored in the buffer into the specified page in the main memory. the page in main memory that is being programmed must have been previously erased using one of the erase commands (page erase, block erase, sector erase, or chip erase). the programming of the page is internally self-timed and should take place in a maximum time of t p . during this time, the rdy/ busy bit in the status register will indicate that the device is busy.
11 at45db021e 8789e?dflash?10/2013 the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. 6.4 main memory page program through buffer with built-in erase the main memory page program through buffer with built-in erase command combines the buffer write and buffer to main memory page program with built-in erase operations into a single operation to help simplify application firmware development. with the main memory page program through buffer with built-in erase command, data is first clocked into the buffer, the addressed page in memory is then automatically erased, and then the contents of the buffer are programmed into the just-erased main memory page. to perform a main memory page program through buffer using the standard dataflash page size (264 bytes), an opcode of 82h must first be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9 - pa0) that specify the page in the main memory to be written, and nine buffer address bits (bfa8 - bfa0) that select the first byte in the buffer to be written. to perform a main memory page program through buffer using the binary page size (256 bytes), an opcode of 82h must first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) that specify the page in the main memory to be written, and eight address bits (a7 - a0) that selects the first byte in the buffer to be written. after all address bytes have been clocked in, the device will take data from the input pin (si) and store it in the buffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the device will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into that main memory page. both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates intelligent erase and programming algorithms that can detect when a byte location fails to erase or program properly. if an erase or program error arises, it will be indicated by the epe bit in the status register. 6.5 main memory byte/page program through buffer without built-in erase the main memory byte/page program through the buffer without built-in erase combines both the buffer write and buffer to main memory program without built-in erase operations to allow any number of bytes (1 to 256/264 bytes) to be programmed directly into previously erased locations in the main memory array. with the main memory byte/page program through buffer without built-in erase command, data is first clocked into buffer, and then only the bytes clocked into the buffer are programmed into the pre-erased byte locations in main memory. multiple bytes up to the page size can be entered with one command sequence. to perform a main memory byte/page program through the buffer using the standard dataflash page size (264 bytes), an opcode of 02h must first be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9 - pa0) that specify the page in the main memory to be written, and nine buffer address bits (bfa8 - bfa0) that select the first byte in the buffer to be written. after all address bytes are clocked in, the device will take data from the input pin (si) and store it in the buffer. any number of bytes (1 to 264) can be entered. if the end of the buffer is reached, then the device will wrap around back to the beginning of the buffer. to perform a main memory byte/page program through the buffer using the binary page size (256 bytes), an opcode of 02h must first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (pa9 - pa0) that specify the page in the main memory to be written, and eight address bits (a7 - a0) that selects the first byte in the buffer to be written. after all address bytes are clocked in, the device will take data from the input pin (s i) and store it in the buffer. any number of bytes (1 to 256) can be entered. if the end of the buffer is reached, then the device will wrap around back to the beginning of the buffer. when using the binary page size, the page and buffer address bits correspond to an 18-bit logical address (a17-a0) in the main memory. after all data bytes have been clocked into the device, a low-to-high transition on the cs pin will start the program operation in which the device will program the data stored in the buffer into the main memory array. only the data bytes that were clocked into the device will be programmed into the main memory.
12 at45db021e 8789e?dflash?10/2013 example: if only two data bytes were clocked into the device, then only two bytes will be programmed into main memory and the remaining bytes in the memory page will remain in their previous state. the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise the operation will be aborted and no data will be programmed. the programming of the data bytes is internally self-timed and should take place in a maximum time of t p (the program time will be a multiple of the t bp time depending on the number of bytes being programmed). during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. 6.6 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command or the main memory byte/page program through buffer command to be utilized at a later time. to perform a page erase with the standard dataflash page size (264 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9 - pa0) that specify the page in the main memory to be erased, and nine dummy bits. to perform a page erase with the binary page size (256 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) that specify the page in the main memory to be erased, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the device will erase the selected page (the erased state is a logic 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. 6.7 block erase the block erase command can be used to erase a block of eight pages at one time. this command is useful when needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate page erase commands. to perform a block erase with the standard dataflash page size (264 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of five dummy bits, seven page address bits (pa9 - pa3), and 12 dummy bits. the seven page address bits are used to specify which block of eight pages is to be erased. to perform a block erase with the binary page size (256 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of six dummy bits, seven page address bits (a17 - a11), and 11 dummy bits. the seven page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the device will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register.
13 at45db021e 8789e?dflash?10/2013 table 6-1. block erase addressing 6.8 sector erase the sector erase command can be used to individually erase any sector in the main memory. the main memory array is comprised of nine sectors, and only one sector can be erased at a time. to perform an erase of sector 0a or sector 0b with the standard dataflash page size (264 bytes), an opcode of 7ch must be clocked into the device followed by three address bytes comprised of five dummy bits, seven page address bits (pa9 - pa3), and 12 dummy bits. to perform a sector 1-7 erase, an opcode of 7ch must be clocked into the device followed by three address bytes comprised of five dummy bits, three page address bits (pa9 - pa7), and 16 dummy bits. to perform a sector 0a or sector 0b erase with the binary page size (256 bytes), an opcode of 7ch must be clocked into the device followed by three address bytes comprised of six dummy bits, seven page address bits (a17 - a11), and 11 dummy bits. to perform a sector 1-7 erase, an opcode of 7ch must be clocked into the device followed by six dummy bits, three page address bits (a17 - a15), and 15 dummy bits. the page address bits are used to specify any valid address location within the sector is to be erased. when a low-to-high transition occurs on the cs pin, the device will erase the selected sector. the erase operation is internally self-timed and should take place in a maximum time of t se . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. pa9/a17 pa8/a16 pa7/a15 pa6/a14 pa5/a13 pa4/a12 pa3/a11 pa2/a10 pa1/a9 pa0/a8 block 0 0 0 0 0 0 0 x x x 0 0 0 0 0 0 0 1 x x x 1 0 0 0 0 0 1 0 x x x 2 0 0 0 0 0 1 1 x x x 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 0 0 x x x 124 1 1 1 1 1 0 1 x x x 125 1 1 1 1 1 1 0 x x x 126 1 1 1 1 1 1 1 x x x 127
14 at45db021e 8789e?dflash?10/2013 table 6-2. sector erase addressing 6.9 chip erase the chip erase command allows the entire main memory array to be erased at one time. to execute the chip erase command, a 4-byte command sequence of c7h, 94h, 80h, and 9ah must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device and any data clocked in after the opcode will be ignored. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to start the erase process. the erase operation is internally self-timed and should take place in a time of t ce . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the chip erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. only those sectors that are not protected or locked down will be erased. the wp pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. table 6-3. chip erase command figure 6-1. chip erase pa9/a17 pa8/a16 pa7/a15 pa6/a14 pa5/a13 pa4/a12 pa3/a11 pa2/a10 pa1/a9 pa0/a8 sector 0 0 0 0 0 0 0 x x x 0a 0 0 0 0 0 0 1 x x x 0b 0 0 1 x x x x x x x 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 1 x x x x x x x 5 1 1 0 x x x x x x x 6 1 1 1 x x x x x x x 7 command byte 1 byte 2 byte 3 byte 4 chip erase c7h 94h 80h 9ah c7h 94h 80h 9ah cs each transition represents eight bits
15 at45db021e 8789e?dflash?10/2013 6.10 read-modify-write a completely self-contained read-modify-write operation can be performed to reprogram any number of sequential bytes in a page in the main memory array without affecting the rest of the bytes in the same page. this command allows the device to easily emulate an eeprom by providing a method to modify a single byte or more in the main memory in a single operation, without the need for pre-erasing the memory or the need for any external ram buffers. the read-modify-write command is essentially a combination of the main memory page to buffer transfer, buffer write, and buffer to main memory page program with built-in erase commands. to perform a read-modify-write using the standard dataflash page size (264 bytes), an opcode of 58h for buffer 1 or 59h for buffer 2 must be clocked into the device followed by three address bytes comprised of four dummy bits, 11 page address bits (pa10 - pa0) that specify the page in the main memory to be written, and nine byte address bits (ba8 - ba0) that designate the starting byte address within the page to reprogram. to perform a read-modify-write using the binary page size (256 bytes), an opcode of 58h for buffer 1 or 59h for buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 11 page address bits (a18 - a8) that specify the page in the main memory to be written, and eight byte address bits (a7 - a0) designate the starting byte address within the page to reprogram. after the address bytes have been clocked in, any number of sequential data bytes from one to 256/264 bytes can be clocked into the device. if the end of the buffer is reached when clocking in the data, then the device will wrap around back to the beginning of the buffer. after all data bytes have been clocked into the device, a low-to-high transition on the cs pin will start the self-contained, internal read-modify-write operation. only the data bytes that were clocked into the device will be reprogrammed in the main memory. example: if only one data byte was clocked into the device, then only one byte in main memory will be reprogrammed and the remaining bytes in the main memory page will remain in their previous state. the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and no data will be programmed. the reprogramming of the data bytes is internally self-timed and should take place in a maximum time of t p . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to erase or program properly. if an erase or program error arises, it will be indicated by the epe bit in the status register. note: the read-modify-write command uses the same opcodes as the auto page rewrite command. if no data bytes are clocked into the device, then the device will perform an auto page rewrite operation. see the auto page rewrite command description on page 25 for more details.
16 at45db021e 8789e?dflash?10/2013 7. sector protection two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. the software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the write protect ( wp) pin. the selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile sector protection register. the status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be determined by checking the status register. 7.1 software sector protection software controlled protection is useful in applications in which the wp pin is not or cannot be controlled by a host processor. in such instances, the wp pin may be left floating (the wp pin is internally pulled high) and sector protection can be controlled using the enable sector protection and disable sector protection commands. if the device is power cycled, then the software controlled protection will be disabled. once the device is powered up, the enable sector protection command should be reissued if sector protection is desired and if the wp pin is not used. 7.1.1 enable sector protection sectors specified for protection in the sector protection register can be protected from program and erase operations by issuing the enable sector protection command. to enable the sector protection, a 4-byte command sequence of 3dh, 2ah, 7fh, and a9h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to enable the sector protection. table 7-1. enable sector protection command figure 7-1. enable sector protection 7.1.2 disable sector protection to disable the sector protection, a 4-byte command sequence of 3dh, 2ah, 7fh, and 9ah must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to disable the sector protection. table 7-2. disable sector protection command figure 7-2. disable sector protection command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h 3dh 2ah 7fh 9ah cs each transition represents eight bits si command byte 1 byte 2 byte 3 byte 4 disable sector protection 3dh 2ah 7fh 9ah 3dh 2ah 7fh 9ah cs each transition represents eight bits si
17 at45db021e 8789e?dflash?10/2013 7.2 hardware controlled protection sectors specified for protection in the sector protection register and the sector protection register itself can be protected from program and erase operations by asserting the wp pin and keeping the pin in its asserted state. the sector protection register and any sector specified for protection cannot be erased or programmed as long as the wp pin is asserted. in order to modify the sector protection register, the wp pin must be deasserted. if the wp pin is permanently connected to gnd, then the contents of the sector protection register cannot be changed. if the wp pin is deasserted or permanently connected to v cc , then the contents of the sector protection register can be modified. the wp pin will override the software controlled protection method but only for protecting the sectors. example: if the sectors were not previously protected by the enable sector protection command, then simply asserting the wp pin would enable the sector protection within the maximum specified t wpe time. when the wp pin is deasserted, however, the sector protection would no longer be enabled (after the maximum specified t wpd time) as long as the enable sector protection command was not issued while the wp pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deasserting the wp pin would not disable the sector protection. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sector protection. the disable sector protection command is also ignored whenever the wp pin is asserted. a noise filter is incorporated to help protect against spurious noise that my inadvertently assert or deassert the wp pin. figure 7-3 and table 7-3 detail the sector protection status for various scenarios of the wp pin, the enable sector protection command, and the disable sector protection command. figure 7-3. wp pin and protection status table 7-3. wp pin and protection status time period wp pin enable sector protection command disable sector protection command sector protection status sector protection register 1 high command not issued previously x disabled read/write ? issue command disabled read/write issue command ? enabled read/write 2 low x x enabled read 3 high command issued during period 1 or 2 not issued yet enabled read/write ? issue command disabled read/write issue command ? enabled read/write wp 12 3
18 at45db021e 8789e?dflash?10/2013 7.3 sector protection register the nonvolatile sector protection register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. the sector protection register contains eight bytes of data, of which byte locations 0 through 7 contain values that specify whether sectors 0 through 7 will be protected or unprotected. the sector protection register is user modifiable and must be erased before it can be reprogrammed. table 7-4 illustrates the format of the sector protection register. table 7-4. sector protection register note: 1. the default values for bytes 0 through 7 are 00h when shipped from adesto. table 7-5. sector 0 (0a, 0b) sector protection register byte value note: 1. x = don?t care 7.3.1 erase sector protection register in order to modify and change the values of the sector protection register, it must first be erased using the erase sector protection register command. to erase the sector protection register, a 4-byte command sequence of 3dh, 2ah, 7fh, and cfh must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed erase cycle. the erasing of the sector protection register should take place in a maximum time of t pe . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. if the device is powered-down before the completion of the erase cycle, then the contents of the sector protection register cannot be guaranteed. the sector protection register can be erased with sector protection enabled or disabled. since the erased state (ffh) of each byte in the sector protection register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. if for some reason an erroneous program or erase command is sent to the device immediately after erasing the sector protection register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. table 7-6. erase sector protection register command sector number 0 (0a, 0b) 1 to 7 protected see table 7-5 ffh unprotected 00h bit 7:6 bit 5:4 bit 3:2 bit 1:0 data value sector 0a (page 0-7) sector 0b (page 8-127) n/a n/a sectors 0a and 0b unprotected 00 00 xx xx 0xh protect sector 0a 11 00 xx xx cxh protect sector 0b 00 11 xx xx 3xh protect sectors 0a and 0b 11 11 xx xx fxh command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh
19 at45db021e 8789e?dflash?10/2013 figure 7-4. erase sector protection register 7.3.2 program sector protection register once the sector protection register has been erased, it can be reprogrammed using the program sector protection register command. to program the sector protection register, a 4-byte command sequence of 3dh, 2ah, 7fh, and fch must be clocked into the device followed by eight bytes of data corresponding to sectors 0 through 7. after the last bit of the opcode sequence and data have been clocked in, the cs pin must be deasserted to initiate the internally self-timed program cycle. the programming of the sector protection register should take place in a maximum time of t p . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. if the device is powered-down before the completion of the erase cycle, then the contents of the sector protection register cannot be guaranteed. if the proper number of data bytes is not clocked in before the cs pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in cannot be guaranteed. example: if only the first two bytes are clocked in instead of the complete eight bytes, then the protection status of the last six sectors cannot be guaranteed. furthermore, if more than eight bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if nine bytes of data are clocked in, then the ninth byte will be stored at byte location 0 of the sector protection register. the data bytes clocked into the sector protection register need to be valid values (0xh, 3xh, cxh, and fxh for sector 0a or sector 0b, and 00h or ffh for other sectors) in order for the protection to function correctly. if a non-valid value is clocked into a byte location of the sector protection register, then the protection status of the sector corresponding to that byte location cannot be guaranteed. example: if a value of 17h is clocked into byte location 2 of the sector protection register, then the protection status of sector 2 cannot be guaranteed. the sector protection register can be reprogrammed while the sector protection is enabled or disabled. being able to reprogram the sector protection register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling sector protection completely. the program sector protection register command utilizes the internal buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. table 7-7. program sector protection register command figure 7-5. program sector protection register 3dh 2ah 7fh cfh cs each transition represents eight bits si command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch data byte n 3dh 2ah 7fh fch data byte n + 1 cs each transition represents eight bits si data byte n + 7
20 at45db021e 8789e?dflash?10/2013 7.3.3 read sector protection register to read the sector protection register, an opcode of 32h and three dummy bytes must be clocked into the device. after the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the sck pin will result in the sector protection register contents being output on the so pin. the first byte (byte location 0) corresponds to sector 0 (0a and 0b), the second byte corresponds to sector 1, and the last byte (byte location 7) corresponds to sector 7. once the last byte of the sector protection register has been clocked out, any additional clock pulses will result in undefined data being output on the so pin. the cs pin must be deasserted to terminate the read sector protection register operation and put the output into a high-impedance state. table 7-8. read sector protection register command note: 1. xx = dummy byte figure 7-6. read sector protection register 7.3.4 about the sector protection register the sector protection register is subject to a limit of 10,000 erase/program cycles. users are encouraged to carefully evaluate the number of times the sector protection register will be modified during the course of the application?s life cycle. if the application requires that the security protection register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the sector protection register is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. command byte 1 byte 2 byte 3 byte 4 read sector protection register 32h xxh xxh xxh 32h xx xx xx data n data n + 1 cs si so each transition represents eight bits data n + 7
21 at45db021e 8789e?dflash?10/2013 8. security features 8.1 sector lockdown the device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read-only (rom). this is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. warning: once a sector is locked down, it can never be erased or programmed, and it can never be unlocked. to issue the sector lockdown command, a 4-byte command sequence of 3dh, 2ah, 7fh, and 30h must be clocked into the device followed by three address bytes specifying any address within the sector to be locked down. after the last address bit has been clocked in, the cs pin must be deasserted to initiate the internally self-timed lockdown sequence. the lockdown sequence should take place in a maximum time of t p . during this time, the rdy/ busy bit in the status register will indicate that the device is busy. if the device is powered-down before the completion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. in this case, it is recommended that the user read the sector lockdown register to determine the status of the appropriate sector lockdown bits or bytes and re-issue the sector lockdown command if necessary. table 8-1. sector lockdown command figure 8-1. sector lockdown 8.1.1 read sector lockdown register the nonvolatile sector lockdown register specifies which sectors in the main memory are currently unlocked or have been permanently locked down. the sector lockdown register is a read-only register and contains eight bytes of data which correspond to sectors 0 through 7. to read the sector lockdown register, an opcode of 35h must be clocked into the device followed by three dummy bytes. after the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the sector lockdown register will be clocked out on the so pin. the first byte (byte location 0) corresponds to sector 0 (0a and 0b), the second byte corresponds to sector 1, and the last byte (byte location 7) corresponds to sector 7. after the last byte of the sector lockdown register has been read, additional pulses on the sck pin will result in undefined data being output on the so pin. deasserting the cs pin will terminate the read sector lockdown register operation and put the so pin into a high-impedance state. table 8-2 details the format the sector lockdown register. table 8-2. sector lockdown register command byte 1 byte 2 byte 3 byte 4 sector lockdown 3dh 2ah 7fh 30h 3dh 2ah 7fh 30h cs address byte address byte address byte si each transition represents eight bits sector number 0 (0a, 0b) 1 to 7 locked see table 8-3 ffh unlocked 00h
22 at45db021e 8789e?dflash?10/2013 table 8-3. sector 0 (0a and 0b) sector lockdown register byte value table 8-4. read sector lockdown register command figure 8-2. read sector lockdown register 8.1.2 freeze sector lockdown the sector lockdown command can be permanently disabled, and the current sector lockdown state can be permanently frozen so that no additional sectors can be locked down aside from those already locked down. any attempts to issue the sector lockdown command after the sector lockdown state has been frozen will be ignored. to issue the freeze sector lockdown command, the cs pin must be asserted and the opcode sequence of 34h, 55h, aah, and 40h must be clocked into the device. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the current sector lockdown state will be permanently frozen within a time of t lock . in addition, the sle bit in the status register will be permanently reset to a logic 0 to indicate that the sector lockdown command is permanently disabled. table 8-5. freeze sector lockdown figure 8-3. freeze sector lockdown bit 7:6 bit 5:4 bit 3:2 bit 1:0 data value sector 0a (page 0-7) sector 0b (page 8-127) n/a n/a sectors 0a and 0b unlocked 00 00 00 00 00h sector 0a locked 11 00 00 00 c0h sector 0b locked 00 11 00 00 30h sectors 0a and 0b locked 11 11 00 00 f0h command byte 1 byte 2 byte 3 byte 4 read sector lockdown register 35h xxh xxh xxh 35h xx xx xx data n data n + 1 cs si so each transition represents eight bits data n + 7 command byte 1 byte 2 byte 3 byte 4 freeze sector lockdown 34h 55h aah 40h 34h 55h aah 40h cs si each transition represents eight bits
23 at45db021e 8789e?dflash?10/2013 8.2 security register the device contains a specialized security register that can be used for purposes such as unique device serialization or locked key storage. the register is comprised of a total of 128 bytes that is divided into two portions. the first 64 bytes (byte locations 0 through 63) of the security register are allocated as an one-time programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64 bytes of the register (byte locations 64 through 127) are factory programmed by adesto and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. table 8-6. security register 8.2.1 programming the security register the user programmable portion of the security register does not need to be erased before it is programmed. to program the security register, a 4-byte opcode sequence of 9bh, 00h, 00h, and 00h must be clocked into the device. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the security register must be clocked in. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the internally self-timed program cycle. the programming of the security register should take place in a time of t p , during which time the rdy/ busy bit in the status register will indicate that the device is busy. if the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the security register cannot be guaranteed. if the full 64 bytes of data are not clocked in before the cs pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. example: if only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user programmable portion of the security register cannot be guaranteed. furthermore, if more than 64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for example, if 65 bytes of data are clocked in, then the 65th byte will be stored at byte location 0 of the security register. warning: the user programmable portion of the security register can only be programmed one time. therefore, it is not possible, for example, to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. the program security register command utilizes the internal buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. figure 8-4. program security register security register byte number 0 1 63 64 65 127 data type one-time user programmable factory programmed by adesto data n 9bh 00h 00h 00h data n + 1 data n + 63 cs si each transition represents eight bits
24 at45db021e 8789e?dflash?10/2013 8.2.2 reading the security register to read the security register, an opcode of 77h and three dummy bytes must be clocked into the device. after the last dummy bit has been clocked in, the contents of the security register can be clocked out on the so pin. after the last byte of the security register has been read, additional pulses on the sck pin will result in undefined data being output on the so pin. deasserting the cs pin will terminate the read security register operation and put the so pin into a high-impedance state. figure 8-5. read security register 77h xx xx xx data n data n + 1 cs data n + x si so each transition represents eight bits
25 at45db021e 8789e?dflash?10/2013 9. additional commands 9.1 main memory page to buffer transfer a page of data can be transferred from the main memory to the buffer. to transfer a page of data using the standard dataflash page size (264 bytes), an opcode of 53h must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9 - pa0) which specify the page in main memory to be transferred, and nine dummy bits. to transfer a page of data using the binary page size (256 bytes), an opcode of 53h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) which specify the page in the main memory to be transferred, and eight dummy bits. the cs pin must be low while toggling the sck pin to load the opcode and the three address bytes from the input pin (si). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the page transfer time (t xfr ), the rdy/ busy bit in the status register can be read to determine whether or not the transfer has been completed. 9.2 main memory page to buffer compare a page of data in main memory can be compared to the data in the buffer as a method to ensure that data was successfully programmed after a buffer to main memory page program command. to compare a page of data with the standard dataflash page size (264 bytes), an opcode of 60h must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9 - pa0) which specify the page in the main memory to be compared to the buffer, and nine dummy bits. to compare a page of data with the binary page size (256 bytes), an opcode of 60h must be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits (a17 - a8) which specify the page in the main memory to be compared to the buffer, and eight dummy bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). on the low-to-high transition of the cs pin, the data bytes in the selected main memory page will be compared with the data bytes in the buffer. during the compare time (t comp ), the rdy/ busy bit in the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register will be updated with the result of the compare. 9.3 auto page rewrite this command only needs to be used if the possibility exists that static (non-changing) data may be stored in a page or pages of a sector and the other pages of the same sector are erased and programmed a large number of times. applications that modify data in a random fashion within a sector may fall into this category. to preserve data integrity of a sector, each page within a sector must be updated/rewritten at least once within every 50,000 cumulative page erase/program operations within that sector. the auto page rewrite command provides a simple and efficient method to ?refresh? a page in the main memory array in a single operation. the auto page rewrite command is a combination of the main memory page to buffer transfer and buffer to main memory page program with built-in erase commands. with the auto page rewrite command, a page of data is first transferred from the main memory to the buffer and then the same data is programmed back into the same page of main memory, essentially ?refreshing? the contents of that page. to start the auto page rewrite operation with the standard dataflash page size (264 bytes), a 1-byte opcode, 58h must be clocked into the device followed by three address bytes comprised of five dummy bits, 10 page address bits (pa9-pa0) that specify the page in main memory to be rewritten, and nine dummy bits. to initiate an auto page rewrite with the a binary page size (256 bytes), the opcode 58h must be clocked into the device followed by three address bytes consisting of six dummy bits, 10 page address bits (a17 - a8) that specify the page in the main memory that is to be rewritten, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to the buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/ busy status register will indicate that the part is busy.
26 at45db021e 8789e?dflash?10/2013 if a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be a page or pages of static data, then the programming algorithm shown in figure 26-1 on page 59 is recommended; otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the programming algorithm shown in figure 26-2 on page 60 is recommended. please contact adesto for availability of devices that are specified to exceed the 50,000 cycle cumulative limit. note: the auto page rewrite command uses the same opcodes as the read-modify-write command. if data bytes are clocked into the device, then the device will perform a read-modify-write operation. see the read-modify- write command description on page 15 for more details. 9.4 status register read the 2-byte status register can be used to determine the device's ready/busy status, page size, a main memory page to buffer compare operation result, the sector protection status, freeze sector lockdown status, erase/program error status, and the device density. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and then the opcode d7h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the second byte of the status register has been clocked out, the sequence will repeat itself, starting again with the first byte of the status register, as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence may output new data. the rdy/ busy status is available for both bytes of the status register and is updated for each byte. deasserting the cs pin will terminate the status register read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 9-1. status register format ? byte 1 note: 1. r = readable only bit name type (1) description 7 rdy/ busy ready/busy status r 0 device is busy with an internal operation. 1 device is ready. 6 comp compare result r 0 main memory page data matches buffer data. 1 main memory page data does not match buffer data. 5:2 density density code r 0101 2-mbit 1 protect sector protection status r 0 sector protection is disabled. 1 sector protection is enabled. 0 page size page size configuration r 0 device is configured for standard dataflash page size (264 bytes). 1 device is configured for ?power of 2? binary page size (256 bytes).
27 at45db021e 8789e?dflash?10/2013 table 9-2. status register format ? byte 2 note: 1. r = readable only 9.4.1 rdy/ busy bit the rdy/ busy bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. to poll the rdy/ busy bit to detect the completion of an internally timed operation, new status register data must be continually clocked out of the device until the state of the rdy/ busy bit changes from a logic 0 to a logic 1 to indicate completion. 9.4.2 comp bit the result of the most recent main memory page to buffer compare operation is indicated using the comp bit. if the comp bit is a logic 1, then at least one bit of the data in the main memory page does not match the data in the buffer. 9.4.3 density bits the device density is indicated using the density bits. for the at45db021e, the four bit binary value is 0101. the decimal value of these four binary bits does not actually equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. the density bits are not the same as the density code indicated in the jedec device id information. the density bits are provided only for backward compatibility to older generation dataflash devices. 9.4.4 protect bit the protect bit provides information to the user on whether or not the sector protection has been enabled or disabled, either by the software-controlled method or the hardware-controlled method. 9.4.5 page size bit the page size bit indicates whether the buffer size and the page size of the main memory array is configured for the ?power of 2? binary page size (256 bytes) or the standard dataflash page size (264 bytes). bit name type (1) description 7 rdy/ busy ready/busy status r 0 device is busy with an internal operation. 1 device is ready. 6 res reserved for future use r 0 reserved for future use. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 res reserved for future use r 0 reserved for future use. 3 sle sector lockdown enabled r 0 sector lockdown command is disabled. 1 sector lockdown command is enabled. 2 res reserved for future use r 0 reserved for future use. 1 res reserved for future use r 0 reserved for future use. 0 res reserved for future use r 0 reserved for future use.
28 at45db021e 8789e?dflash?10/2013 9.4.6 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logic 1 state. the epe bit will not be set if an erase or program operation aborts for any reason, such as an attempt to erase or program a protected region. the epe bit is updated after every erase and program operation. 9.4.7 sle bit the sle bit indicates whether or not the sector lockdown command is enabled or disabled. if the sle bit is a logic 1, then the sector lockdown command is still enabled and sectors can be locked down. if the sle bit is a logic 0, then the sector lockdown command has been disabled and no further sectors can be locked down.
29 at45db021e 8789e?dflash?10/2013 10. deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. when the device is in the deep power-down mode, all commands including the status register read command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 10-1. deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd
30 at45db021e 8789e?dflash?10/2013 10.1 resume from deep power-down in order to exit the deep power-down mode and resume normal device operation, the resume from deep power-down command must be issued. the resume from deep power-down command is the only command that the device will recognize while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and then the opcode abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode and return to the standby mode within the maximum time of t rdpd . after the device has returned to the standby mode, normal command operations such as continuous array read can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, then the device will abort the operation and return to the deep power-down mode. figure 10-2. resume from deep power-down sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
31 at45db021e 8789e?dflash?10/2013 10.2 ultra-deep power-down the ultra-deep power-down mode allows the device to consume far less power compared to the standby and deep power-down modes by shutting down additional internal circuitry. since almost all active circuitry is shut down in this mode to conserve power, the contents of the buffer cannot be maintained. therefore, any data stored in the buffer will be lost once the device enters the ultra-deep power-down mode. when the device is in the ultra-deep power-down mode, all commands including the status register read and resume from deep power-down commands will be ignored. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the ultra-deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode 79h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the ultra-deep power-down mode within the maximum time of t eudpd . the complete opcode must be clocked in before the cs pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the ultra-deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the ultra-deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the ultra-deep power-down mode. figure 10-3. ultra-deep power-down sck cs si so msb i cc 23 1 0 0 67 5 4 opcode high-impedance ultra-deep power-down mode current active current standby mode current t eudpd 1111001
32 at45db021e 8789e?dflash?10/2013 10.2.1 exit ultra-deep power-down to exit from the ultra-deep power-down mode, the cs pin must simply be pulsed by asserting the cs pin, waiting the minimum necessary t cslu time, and then deasserting the cs pin again. to facilitate simple software development, a dummy byte opcode can also be entered while the cs pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case. after the cs pin has been deasserted, the device will exit from the ultra-deep power-down mode and return to the standby mode within a maximum time of t xudpd . if the cs pin is reasserted before the t xudpd time has elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will be performed. the system must wait for the device to return to the standby mode before normal command operations such as continuous array read can be resumed. since the contents of the buffer cannot be maintained while in the ultra-deep power-down mode, the buffer will contain undefined data when the device returns to the standby mode. figure 10-4. exit ultra-deep power-down cs so i cc high-impedance ultra-deep power-down mode current active current standby mode current t xudpd t cslu
33 at45db021e 8789e?dflash?10/2013 11. buffer and page size configuration the memory array of dataflash devices is actually larger than other serial flash devices in that extra user-accessible bytes are provided in each page of the memory array. for the at45db021e, there are an extra eight bytes of memory in each page for a total of an extra 8kb (64-kbits) of user-accessible memory. some applications, however, may not want to take advantage of this extra memory and instead architect their software to operate on a ?power of 2? binary, logical addressing scheme. to allow this, the dataflash can be configured so that the buffer and page sizes are 256 bytes instead of the standard 264 bytes. in addition, the configuration of the buffer and page sizes is reversible and can be changed from 264 bytes to 256 bytes or from 256 bytes to 264 bytes. the configured setting is stored in an internal nonvolatile register so that the buffer and page size configuration is not affected by power cycles. the nonvolatile register has a limit of 10,000 erase/program cycles; therefore, care should be taken to not switch between the size options more than 10,000 times. devices are initially shipped from adesto with the buffer and page sizes set to 264 bytes. devices can be ordered from adesto pre-configured for the ?power of 2? binary size of 256 bytes. for details, see section 27., "ordering information" on page 61 . to configure the device for ?power of 2? binary page size (256 bytes), a 4-byte opcode sequence of 3dh, 2ah, 80h, and a6h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. the programming of the nonvolatile register should take place in a time of t ep , during which time, the rdy/ busy bit in the status register will indicate that the device is busy. the device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 256 bytes. to configure the device for standard dataflash page size (264 bytes), a 4-byte opcode sequence of 3dh, 2ah, 80h, and a7h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. the programming of the nonvolatile register should take place in a time of t ep , during which time, the rdy/ busy bit in the status register will indicate that the device is busy. the device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 264 bytes. table 11-1. buffer and page size configuration commands figure 11-1. buffer and page size configuration command byte 1 byte 2 byte 3 byte 4 ?power of 2? binary page size (256 bytes) 3dh 2ah 80h a6h dataflash page size (264 bytes) 3dh 2ah 80h a7h cs si 3dh 2ah 80h opcode byte 4 each transition represents eight bits
34 at45db021e 8789e?dflash?10/2013 12. manufacturer and device id read identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec-defined manufacturer id, the vendor-specific device id, and the vendor-specific extended device information. the read manufacturer and device id command is limited to a maximum clock frequency of f clk . since not all flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. once the identification process is complete, the application can then increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted, and then the opcode 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte to be output will be the manufacturer id, followed by two bytes of the device id information. the fourth byte output will be the extended device information (edi) string length, which will be 01h, indicating that one byte of edi data follows. after the one byte of edi data is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the edi string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (byte 1) 23h 3 device id (byte 2) 00h 4 [optional to read] extended device information (edi) string length 01h 5 [optional to read] edi byte 1 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 0 0 0 1 1 1 1 1 device id (byte 1) family code density code 23h family code: 001 (at45dxxx family) density code: 00011 (2-mbit) 0 0 1 0 0 0 1 1 device id (byte 2) sub code product variant 00h sub code: 000 (standard series) product variant:00000 0 0 0 0 0 0 0 0
35 at45db021e 8789e?dflash?10/2013 figure 12-1. read manufacturer and device id table 12-3. edi data byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details 1 rfu device revision 00h rfu: reserved for future use device revision:00000 (initial version) 0 0 0 0 0 0 0 0 sck cs si so 6 0 9fh 8 7 46 opcode 1fh 00h 01h 00h manufacturer id device id byte 1 device id byte 2 edi string length edi data byte 1 high-impedance 14 16 15 22 24 23 38 40 39 30 32 31 note: each transition shown for si and so represents one byte (eight bits) 23h
36 at45db021e 8789e?dflash?10/2013 13. software reset in some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. the software reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. to perform a software reset, the cs pin must be asserted and a 4-byte command sequence of f0h, 00h, 00h, and 00h must be clocked into the device. any additional data clocked into the device after the last byte will be ignored. when the cs pin is deasserted, the program or erase operation currently in progress will be terminated within a time t swrst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or erased cannot be guaranteed to be valid. the software reset command has no effect on the states of the sector protection register, the sector lockdown register, or the buffer and page size configuration. the complete 4-byte opcode must be clocked into the device before the cs pin is deasserted; otherwise, no reset operation will be performed. table 13-1. software reset figure 13-1. software reset command byte 1 byte 2 byte 3 byte 4 software reset f0h 00h 00h 00h cs si f0h 00h 00h 00h each transition represents eight bits
37 at45db021e 8789e?dflash?10/2013 14. operation mode summary the commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. group a commands consist of: 1. main memory page read 2. continuous array read (spi) 3. read sector protection register 4. read sector lockdown register 5. read security register 6. buffer read group b commands consist of: 1. page erase 2. block erase 3. sector erase 4. chip erase 5. main memory page to the buffer transfer 6. main memory page to the buffer compare 7. buffer to main memory page program with built-in erase 8. buffer to main memory page program without built-in erase 9. main memory page program through the buffer with built-in erase 10. main memory byte/page program through buffer without built-in erase 11. auto page rewrite group c commands consist of: 1. buffer write 2. status register read 3. manufacturer and device id read group d commands consist of: 1. erase sector protection register 2. program sector protection register 3. sector lockdown 4. program security register 5. buffer and page size configuration 6. freeze sector lockdown if a group a command is in progress (not fully completed), then another command in group a, b, c, or d should not be started. however, during the internally self-timed portion of group b commands, any command in group c can be executed. the group b commands using the buffer should use group c commands . finally, during the internally self-timed portion of a group d command, only the status register read command should be executed.
38 at45db021e 8789e?dflash?10/2013 15. command tables table 15-1. read commands table 15-2. program and erase commands command opcode main memory page read d2h continuous array read (low power mode) 01h continuous array read (low frequency) 03h continuous array read (high frequency) 0bh continuous array read (legacy command ? not recommended for new designs) e8h buffer read (low frequency) d1h buffer read (high frequency) d4h command opcode buffer write 84h buffer to main memory page program with built-in erase 83h buffer to main memory page program without built-in erase 88h main memory page program through buffer with built-in erase 82h main memory byte/page program through buffer without built-in erase 02h page erase 81h block erase 50h sector erase 7ch chip erase c7h + 94h + 80h + 9ah
39 at45db021e 8789e?dflash?10/2013 table 15-3. protection and security commands table 15-4. additional commands table 15-5. legacy commands (1) note: 1. legacy commands are not recommended for new designs. command opcode enable sector protection 3dh + 2ah + 7fh + a9h disable sector protection 3dh + 2ah + 7fh + 9ah erase sector protection register 3dh + 2ah + 7fh + cfh program sector protection register 3dh + 2ah + 7fh + fch read sector protection register 32h sector lockdown 3dh + 2ah + 7fh + 30h read sector lockdown register 35h freeze sector lockdown 34h + 55h + aah + 40h program security register 9bh + 00h + 00h + 00h read security register 77h command opcode main memory page to buffer transfer 53h main memory page to buffer compare 60h auto page rewrite or read modify write through buffer 58h deep power-down b9h resume from deep power-down abh ultra-deep power-down 79h status register read d7h manufacturer and device id read 9fh configure ?power of 2? (binary) page size 3dh + 2ah + 80h + a6h configure standard dataflash page size 3dh + 2ah + 80h + a7h software reset f0h + 00h + 00h + 00h command opcode buffer read 54h main memory page read 52h continuous array read 68h status register read 57h
40 at45db021e 8789e?dflash?10/2013 table 15-6. detailed bit-level addressing sequence for binary page size (256 bytes) note: x = dummy bit page size = 256-bytes address byte address byte address byte additional dummy bytes opcode opcode reserved reserved reserved reserved reserved reserved a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01h 0 0 0 0 0 0 0 1 x x x x x x a a a a a a a a a a a a a a a a a a n/a 02h 0 0 0 0 0 0 1 0 x x x x x x a a a a a a a a a a a a a a a a a a n/a 03h 0 0 0 0 0 0 1 1 x x x x x x a a a a a a a a a a a a a a a a a a n/a 0bh 0 0 0 0 1 0 1 1 x x x x x x a a a a a a a a a a a a a a a a a a 1 1bh 0 0 0 1 1 0 1 1 x x x x x x a a a a a a a a a a a a a a a a a a 2 32h 0 0 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x n/a 35h 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 50h 0 1 0 1 0 0 0 0 x x x x x x a a a a a a x x x x x x x x x x x x n/a 53h 0 1 0 1 0 0 1 1 x x x x x x a a a a a a a a a x x x x x x x x x n/a 58h 0 1 0 1 1 0 0 0 x x x x x x a a a a a a a a a x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 x x x x x x a a a a a a a a a x x x x x x x x x n/a 77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 79h 0 1 1 1 1 0 0 1 n/a n/a n/a n/a 7ch 0 1 1 1 1 1 0 0 x x x x x x a a a x x x x x x x x x x x x x x x n/a 81h 1 0 0 0 0 0 0 1 x x x x x x a a a a a a a a a x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 x x x x x x a a a a a a a a a a a a a a a a a a n/a 83h 1 0 0 0 0 0 1 1 x x x x x x a a a a a a a a a x x x x x x x x x n/a 84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a n/a 88h 1 0 0 0 1 0 0 0 x x x x x x a a a a a a a a a x x x x x x x x x n/a 9fh 1 0 0 1 1 1 1 1 n/a n/a n/a n/a b9h 1 0 1 1 1 0 0 1 n/a n/a n/a n/a abh 1 0 1 0 1 0 1 1 n/a n/a n/a n/a d1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a d2h 1 1 0 1 0 0 1 0 x x x x x x a a a a a a a a a a a a a a a a a a 4 d4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a 1 d7h 1 1 0 1 0 1 1 1 n/a n/a n/a n/a e8h 1 1 1 0 1 0 0 0 x x x x x x a a a a a a a a a a a a a a a a a a 4
41 at45db021e 8789e?dflash?10/2013 table 15-7. detailed bit-level addressing sequence for standard dataflash page size (264 bytes) note: p = page address bit b = byte/buffer address bit x = dummy bit page size = 264-bytes address byte address byte address byte additional dummy bytes opcode opcode reserved reserved reserved reserved reserved pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 01h 0 0 0 0 0 0 0 1 x x x x x p p p p p p p p p p b b b b b b b b b n/a 02h 0 0 0 0 0 0 1 0 x x x x x p p p p p p p p p p b b b b b b b b b n/a 03h 0 0 0 0 0 0 1 1 x x x x x p p p p p p p p p p b b b b b b b b b n/a 0bh 0 0 0 0 1 0 1 1 x x x x x p p p p p p p p p p b b b b b b b b b 1 1bh 0 0 0 1 1 0 1 1 x x x x x p p p p p p p p p p b b b b b b b b b 2 32h 0 0 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x n/a 35h 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 50h 0 1 0 1 0 0 0 0 x x x x x p p p p p p p x x x x x x x x x x x x n/a 53h 0 1 0 1 0 0 1 1 x x x x x p p p p p p p p p p x x x x x x x x x n/a 58h 0 1 0 1 1 0 0 0 x x x x x p p p p p p p p p p x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 x x x x x p p p p p p p p p x x x x x x x x x x n/a 77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 79h 0 1 1 1 1 0 0 1 n/a n/a n/a n/a 7ch 0 1 1 1 1 1 0 0 x x x x x p p p x x x x x x x x x x x x x x x x n/a 81h 1 0 0 0 0 0 0 1 x x x x x p p p p p p p p p p x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 x x x x x p p p p p p p p p p b b b b b b b b b n/a 83h 1 0 0 0 0 0 1 1 x x x x x p p p p p p p p p p x x x x x x x x x n/a 84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x x b b b b b b b b b n/a 88h 1 0 0 0 1 0 0 0 x x x x x p p p p p p p p p p x x x x x x x x x n/a 9fh 1 0 0 1 1 1 1 1 n/a n/a n/a n/a b9h 1 0 1 1 1 0 0 1 n/a n/a n/a n/a abh 1 0 1 0 1 0 1 1 n/a n/a n/a n/a d1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x b b b b b b b b b n/a d2h 1 1 0 1 0 0 1 0 x x x x x p p p p p p p p p p b b b b b b b b b 4 d4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x x b b b b b b b b b 1 d7h 1 1 0 1 0 1 1 1 n/a n/a n/a n/a e8h 1 1 1 0 1 0 0 0 x x x x x p p p p p p p p p p b b b b b b b b b 4
42 at45db021e 8789e?dflash?10/2013 16. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to spi mode 3. in addition, the output pin (so) will be in a high-impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the spi mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. 16.1 initial power-up timing restrictions during power-up, the device must not be accessed for at least the minimum t vcsl time after the supply voltage reaches the minimum v cc level. while the device is being powered-up, the internal power-on reset (por) circuitry keeps the device in a reset mode until the supply voltage rises above the maximum por threshold value (v por ). during this time, all operations are disabled, and the device will not respond to any commands. after power-up, the device will be in the standby mode. if the first operation to the device after power-up will be a program or erase operation, then the operation cannot be started until the supply voltage reaches the minimum v cc level and an internal device delay has elapsed. this delay will be a maximum time of t puw . table 16-1. power-up timing figure 16-1. power-up timing symbol parameter min max units t vcsl minimum v cc to chip select low time 70 s t puw power-up device delay before program or erase allowed 3 ms v por power-on reset (por) voltage 1.45 1.60 v program/erase operations permitted read operation permitted v cc v cc (min) v por (max) v por (min) time do not attempt device access during this time t puw t vcsl
43 at45db021e 8789e?dflash?10/2013 17. system considerations the serial interface is controlled by the serial clock (sck), serial input (si), and chip select ( cs) pins. these signals must rise and fall monotonically and be free from noise. excessive noise or ringing on these pins can be misinterpreted as multiple edges and will cause improper operation of the device. pcb traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash devices occurs during the programming and erasing operations. the supply voltage regulator needs to be able to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, current starvation during programming or erasing can lead to improper operation and possible data corruption.
44 at45db021e 8789e?dflash?10/2013 18. electrical specifications 18.1 absolute maximum ratings* 18.2 dc and ac operating range temperature under bias-55c to +125c storage temperature-65c to +150c all input voltages (except v cc but including nc pins) with respect to ground-0.6v to +6.25v all output voltages with respect to ground-0.6v to v cc + 0.6v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. the ?absolute maximum ratings? are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. at45db021e operating temperature (case) industrial -40 ? c to 85 ? c v cc power supply 1.65v to 3.6v
45 at45db021e 8789e?dflash?10/2013 18.3 dc characteristics notes: 1. typical values measured at 1.8v @ 25 c for the 1.65v to 3.6v range. 2. typical values measured at 3.0v @ 25 c for the 2.3v to 3.6v range. 3. all inputs (si, sck, cs, wp , and reset) are guaranteed by design to be 5v toleran t. symbol parameter condition 1.65v to 3.6v 2.3v to 3.6v units min typ max min typ max i udpd ultra-deep power- down current all inputs at 0v or v cc 0.2 1 0.35 1 a i dpd deep power-down current cs, reset, wp = v ih all inputs at cmos levels 4.5 12 5 12 a i sb standby current cs, reset, wp = v ih all inputs at cmos levels 25 40 25 40 a i cc1 (1)(2) active current, low power read (01h) operation f = 1mhz; i out = 0ma 6 9 6 9 ma f = 15mhz; i out = 0ma 7 10 7 10 ma i cc2 (1)(2) active current, read operation f = 50mhz; i out = 0ma 10 12 10 12 ma f = 85mhz; i out = 0ma 12 15 12 15 ma i cc3 (1)(2) active current, program operation cs = v cc 10 12 10 12 ma i cc4 (1)(2) active current, erase operation cs = v cc 8 12 8 12 ma i li input load current all inputs at cmos levels 1 1 a i lo output leakage current all inputs at cmos levels 1 1 a v il input low voltage v cc x 0.2 v cc x 0.3 v v ih input high voltage v cc x 0.8 v cc x 0.7 v v ol output low voltage i ol = 100 a 0.2 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v cc - 0.2v v
46 at45db021e 8789e?dflash?10/2013 18.4 ac characteristics note: 1. values are based on device characterization, not 100% tested in production. symbol parameter 1.65v to 3.6v 2.3v to 3.6v min typ max min typ max units f sck sck frequency 70 70 mhz f car1 sck frequency for continuous read 70 85 mhz f car2 sck frequency for continuous read (low frequency) 33 33 mhz f car3 sck frequency for continuous read (low power mode ? 01h opcode) 15 15 mhz t wh sck high time 4 4 ns t wl sck low time 4 4 ns t sckr (1) sck rise time, peak-to-peak 0.1 0.1 v/ns t sckf (1) sck fall time, peak-to-peak 0.1 0.1 v/ns t cs minimum cs high time 20 20 ns t css cs setup time 6 5 ns t csh cs hold time 5 5 ns t su data in setup time 2 2 ns t h data in hold time 1 1 ns t ho output hold time 0 0 ns t dis output disable time 8 6 ns t v output valid 7 6 ns t wpe wp low to protection enabled 1 1 s t wpd wp high to protection disabled 1 1 s t lock freeze sector lockdown time (from cs high) 200 200 s t eudpd cs high to ultra-deep power-down 3 3 s t cslu minimum cs low time to exit ultra-deep power-down 20 20 ns t xudpd exit ultra-deep power-down time 240 120 s t edpd cs high to deep power-down 2 2 s t rdpd resume from deep power-down time 35 35 s t xfr page to buffer transfer time 100 100 s t comp page to buffer compare time 100 100 s t rst reset pulse width 10 10 s t rec reset recovery time 1 1 s t swrst software reset time 35 35 s
47 at45db021e 8789e?dflash?10/2013 18.5 program and erase characteristics 19. input test waveforms and measurement levels 20. output test load symbol parameter typ max typ max units t ep page erase and programming time (256/264 bytes) 10 35 10 25 ms t p page programming time 1.5 3 1.5 3 ms t bp byte programming time 8 8 s t pe page erase time 6 25 6 25 ms t be block erase time 25 35 25 35 ms t se sector erase time 350 550 350 550 ms t ce chip erase time 3 4 3 4 s t otpp otp security register program time 200 500 200 500 s ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2ns (10% to 90%) device under test 30pf 1.65v to 3.6v 2.3v to 3.6v
48 at45db021e 8789e?dflash?10/2013 21. utilizing the rapids function to take advantage of the rapids function?s ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. the dataflash is designed to always clock its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the falling edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latch the incoming data in on the next rising edge of sck. figure 21-1. rapids mode sck mosi miso 1 234567 81 234567 8 mosi = master out, slave in miso = master in, slave out the master is the host controller and the slave is the dataflash. the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out first bit of byte-mosi on the rising edge of sck b. slave clocks in first bit of byte-mosi on the next rising edge of sck c. master clocks out second bit of byte-mosi on the same rising edge of sck d. last bit of byte-mosi is clocked out from the master e. last bit of byte-mosi is clocked into the slave f. slave clocks out first bit of byte-so g. master clocks in first bit of byte-so h. slave clocks out second bit of byte-so i. master clocks in last bit of byte-so a b c d e f g 1 h byte-mosi msb lsb byte-so msb lsb slave cs i
49 at45db021e 8789e?dflash?10/2013 figure 21-2. command sequence for read/write operations for page size 256 bytes (except status register read, manufacturer and device id read) figure 21-3. command sequence for read/write operations for page size 264 bytes (except status register read, manufacturer and device id read) si (input) cmd 8-bits 8-bits 8-bits page address (a17 - a8) x x x x x x x x x x x x x x x x lsb x x x x x x x x byte/buffer address (a7 - a0/bfa7 - bfa0) msb 6 dummy bits page address (pa9 - pa0) byte/buffer address (ba8 - ba0/bfa8 - bfa0) si (input) cmd 8-bits 8-bits 8-bits x x x x x x x x x x x x lsb x x x x x x x x msb 5 dummy bits x x x x
50 at45db021e 8789e?dflash?10/2013 22. ac waveforms four different timing waveforms are shown in figure 22-1 through figure 22-4 . waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. in both cases, output so becomes valid while the sck signal is still low (sck low time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies only up to 70mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and 4 illustrate general timing diagrams for rapids serial interface. these are similar to waveform 1 and 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (maximum frequency = 70mhz) of the rapids serial case. figure 22-1. waveform 1 = spi mode 0 compatible figure 22-2. waveform 2 = spi mode 3 compatible cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high-impedance valid out t ho t dis high-impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high-impedance si
51 at45db021e 8789e?dflash?10/2013 figure 22-3. waveform 3 = rapids mode 0 figure 22-4. waveform 4 = rapids mode 3 cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high-impedance valid out t ho t dis high-impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high-impedance si
52 at45db021e 8789e?dflash?10/2013 23. write operations the following block diagram and waveforms illustrate the various write sequences available. figure 23-1. block diagram figure 23-2. buffer write figure 23-3. buffer to main memory page program flash memory array i/o interface si buffer to main memory page program buffer write page (256/264 bytes) buffer (256/264 bytes) cs si (input) cmd x xx, bfa8 bfa7-0 n n + 1 last byte completes writing into selected buffer binary page size 16 dummy bits + bfa7-bfa0 cs si (input) cmd pa9-7 pa6-0, x xxxx xxx starts self-timed erase/program operation binary page size a17-a8 + 8 dummy bits n = 1st byte read n+1 = 2nd byte read each transition represents eight bits
53 at45db021e 8789e?dflash?10/2013 24. read operations the following block diagram and waveforms illustrate the various read sequences available. figure 24-1. block diagram figure 24-2. main memory page read flash memory array page (256/264 bytes) buffer (256/264 bytes) i/o interface main memory page to buffer main memory page read buffer read so cs si (input) so (output) n cmd pa8-7 pa6-0, ba8 ba7-0 x x address for binary page size a16 a15-a8 a7-a0 n n + 1 4 dummy bytes
54 at45db021e 8789e?dflash?10/2013 figure 24-3. main memory page to buffer transfer data from the selected flash page is read into the buffer figure 24-4. buffer read cs si (input) cmd pa6-0, x xxxx xxxx starts reading page data into buffer binary page size a17-a8 + 8 dummy bits so (output) x ... x, pa9-7 cs si (input) so (output) n cmd x x ... x, bfa8 bfa7-0 x address for binary page size 16 dummy bits + bfa7-bfa0 n n + 1 no dummy byte (opcode d1h) 1 dummy byte (opcode d4h) each transition represents eight bits
55 at45db021e 8789e?dflash?10/2013 25. detailed bit-level read waveforms: rapids mode 0/mode 3 figure 25-1. continuous array read (legacy opcode e8h) figure 25-2. continuous array read (opcode 0bh) figure 25-3. continuous array read (opcode 01h or 03h) s ck cs si so msb msb 2 3 1 0 1 1 1 0 1 0 0 0 6 7 5 4 10 11 9 8 12 63 66 67 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode a a a a a a a a a msb x x x x x x msb msb d d d d d d d d d d address bits 32 dummy bits data byte 1 high-impedance s ck cs si so msb msb 2 3 1 0 0 0 0 0 1 0 1 1 6 7 5 4 10 11 9 8 12 39 42 43 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode a a a a a a a a a msb x x x x x x m s b m s b d d d d d d d d d d address bits a17 - a0 dummy bits data byte 1 high-impedance 36 37 35 x x sck cs si so msb msb 2 3 1 0 0 0 0 0 0 0 1 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode a a a a a a a a a m s b m s b d d d d d d d d d d address bits a17-a0 data byte 1 high-impedance
56 at45db021e 8789e?dflash?10/2013 figure 25-4. main memory page read (opcode d2h) figure 25-5. buffer read (opcode d4h) figure 25-6. buffer read ? low frequency (opcode d1h) sck cs si so msb msb 2 3 1 0 1 1 0 1 0 0 1 0 6 7 5 4 10 11 9 8 12 63 66 67 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode a a a a a a a a a msb x x x x x x msb msb d d d d d d d d d d address bits 32 dummy bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 1 1 0 1 0 1 0 0 6 7 5 4 10 11 9 8 12 39 42 43 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode x x x x a a a x x msb x x x x x x x x msb msb d d d d d d d d d d address bits binary page size = 16 dummy bits + bfa7-bfa0 standard dataflash page size = 15 dummy bits + bfa8-bfa0 dummy bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 1 1 0 1 0 0 0 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x a a a x x msb msb d d d d d d d d d d data byte 1 high-impedance address bits binary page size = 16 dummy bits + bfa7-bfa0 standard dataflash page size = 15 dummy bits + ba8-bfa0
57 at45db021e 8789e?dflash?10/2013 figure 25-7. read sector protection register (opcode 32h) figure 25-8. read sector lockdown register (opcode 35h) figure 25-9. read security register (opcode 77h) sck cs si so msb msb 2 3 1 0 0 0 1 1 0 0 1 0 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x msb msb d d d d d d d d d dummy bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 0 0 1 1 0 1 0 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x m s b m s b d d d d d d d d d dummy bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 0 1 1 1 0 1 1 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x msb msb d d d d d d d d d dummy bits data byte 1 high-impedance
58 at45db021e 8789e?dflash?10/2013 figure 25-10. status register read (opcode d7h) figure 25-11. manufacturer and device read (opcode 9fh) figure 25-12.reset timing note: 1. the cs signal should be in the high state before the reset signal is deasserted. sck cs si so msb 2 3 1 0 1 1 0 1 0 1 1 1 6 7 5 4 10 11 9 8 12 21 22 17 20 19 18 15 16 13 14 23 24 opcode msb msb d d d d d d d d d d msb d d d d d d d d status register data status register data high-impedance sck cs si so 6 0 9fh 8 7 46 opcode 1fh 00h 01h 00h manufacturer id device id byte 1 device id byte 2 edi string length edi data byte 1 high-impedance 14 16 15 22 24 23 38 40 39 30 32 31 note: each transition shown for si and so represents one byte (eight bits) 23h cs sck reset so (output) high-impedance high-impedance si (input) t rst t rec t css
59 at45db021e 8789e?dflash?10/2013 26. auto page rewrite flowchart figure 26-1. algorithm for programming or re-programming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start main memory page program through buffer (82h) end provide address and data buffer write (84h) buffer to main memory page program (83h)
60 at45db021e 8789e?dflash?10/2013 figure 26-2. algorithm for programming or re-programming of the entire array randomly notes: 1. to preserve data integrity, each page of an dataflash sector must be updated/rewritten at least once within every 50,000 cumulative page erase and program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 50,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. start main memory page to buffer transfer (53h) increment page address pointer (2) auto page rewrite (2) (58h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program through buffer (82h) buffer write (84h) buffer to main memory page program (83h)
61 at45db021e 8789e?dflash?10/2013 27. ordering information 27.1 ordering detail device grade h = green, nipdau lead finish, industrial temperature range (?40c to +85c) designator product family device density device revision shipping carrier option package option 02 = 2-mbit interface 1 = serial 45db = dataflash b = bulk (tubes) t = tape and reel y = trays operating voltage n = 1.65v minimum (1.65v to 3.6v) ss = 8-lead, 0.150? narrowde soic s = 8-lead, 0.208? wide soic m = 8-pad, 5 x 6 x 0.6mm udfn at45db021e-sshn-b
62 at45db021e 8789e?dflash?10/2013 27.2 ordering codes (standard dataflash page size) notes: 1. the shipping carrier suffix is not marked on the device. 2. not recommended for new design. use the 8s1 package option. 27.3 ordering codes (binary page mode) notes: 1. the shipping carrier suffix is not marked on the device. 2. not recommended for new design. use the 8s1 package option. 3. parts ordered with suffix code ?2b? are shipped in tape and reel (t&r) with the page size set to 256 bytes. this option is only available for shipping in t&r (-t). ordering code package lead finish operating voltage f sck device grade at45db021e-sshn-b (1) 8s1 nipdau 1.65v to 3.6v 70mhz industrial (-40 ? c to 85 ? c) at45db021e-sshn-t (1) at45db021e-shn-b (1)(2) 8s2 at45db021e-shn-t (1)(2) at45db021e-mhn-y (1) 8ma1 at45db021e-mhn-t (1) ordering code package lead finish operating voltage f sck device grade at45db021e-sshn2b-t (1)(3) 8s1 nipdau 1.65v to 3.6v 70mhz industrial (-40 ? c to 85 ? c) at45db021e-shn2b-t (1)(2)(3) 8s2 at45db021e-mhn2b-t (1)(3) 8ma1 package type 8s1 8-lead 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead 0.208" wide, plastic gull wing small outline (eiaj soic) 8ma1 8-pad (5 x 6 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn)
63 at45db021e 8789e?dflash?10/2013 27.4 ordering codes (reserved) notes: 1. the shipping carrier suffix is not marked on the device. 2. parts ordered with suffix code ?ha? are shipped in tape and reel (t&r) only with the page size set to 264 bytes. 3. parts ordered with suffix code ?hc? are shipped in tape and reel (t&r) only with the page size set to 256 bytes. 4. please contact adesto for a description of these ?reserved? codes. ordering code package lead finish operating voltage f sck device grade at45db021e-sshnha-t (1)(2) 8s1 nipdau 1.65v to 3.6v 70mhz industrial (-40 ? c to 85 ? c) at45db021e-shnha-t (1)(2) 8s2 at45db021e-sshnhc-t (1)(3) 8s1 at45db021e-shnhc-t (1)(3) 8s2 package type 8s1 8-lead 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead 0.208" wide, plastic gull wing small outline (eiaj soic) 8ma1 8-pad (5 x 6 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn)
64 at45db021e 8789e?dflash?10/2013 28. packaging information 28.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: contact@adestotech.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
65 at45db021e 8789e?dflash?10/2013 28.2 8s2 ? 8-lead eiaj soic title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 q 0 8 e 1.27 bsc 3 q q 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
66 at45db021e 8789e?dflash?10/2013 28.3 8ma1 ? 8-pad udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8ma1 yfg d 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max n o t e a 0.45 0.55 0.60 a1 0.00 0.02 0.05 b 0.35 0.40 0.48 c 0.152 ref d 4.90 5.00 5.10 d2 3.80 4.00 4.20 e 5.90 6.00 6.10 e2 3.20 3.40 3.60 e 1.27 l 0.50 0.60 0.75 y 0.00 ? 0.08 k 0.20 ? ? 4/15/08 pin 1 id top view e d a1 a side view y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) 0.45 k pin #1 cham f e r (c 0.35) option a (option b)
67 at45db021e 8789e?dflash?10/2013 29. revision history 30. errata 30.1 no errata conditions doc. rev. date comments 8789e 10/2013 corrected low power read option (up to 15mhz). 8789d 7/2013 updated auto page rewrite cycle to 50,000 cumulative page erase/program operations. added reserved part order codes.updated dc conditions for v ol. 8789c 6/2013 updated electrical and power specifications. removed ccun-t package from ordering codes, (not available with this device). removed references to ubga package (not available with this device). moved ?buffer read? from group c to group a in operation mode summary. removed reference to concurrent read capability. removed preliminary datasheet status. 8789b 11/2012 corrected pinout diagrams to top view. added read-modify-write section. for figures program sector protection register, read sector protection register command, and read sector lockdown register command, changed the opcode from n +15 to n +7. added note at end of section, auto page rewrite. updated figure, exit ultra-deep power-down. in table, additional commands, changed ?auto page rewrite through buffer? to ?auto page rewrite or read modify write through buffer?. power-up timing, increased v por max from 1.55 to 1.60. t xudpd , 1.65v increased maximum 70 s to 120 s and 2.3v maximum from 70 s to 240 s. tse, increased typical from 250ms to 350ms and maximum from 450ms to 550ms. increased 1.65v and 2.3v typical and maximum values for i dpd , i sb , i cc1 , and i cc2 . added legacy commands table. updated datasheet status to preliminary. updated to adesto template. 8789a 05/2012 initial document release.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2013 adesto technologies. all rights reserved. / rev.: 8789e?dflash?10/2013 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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